Designing a video processing architecture requires the consideration of a number of factors. Each functional block of the architecture design must be clearly and precisely defined, as well as the flow of data and control information between the functional blocks. The architecture design must then be mapped into real-life scenarios and applications. The resulting implementation of the architecture design for an actual application must then be evaluated to confirm that the desired performance goals and bandwidth requirements are satisfied.
Typically, a high-level hardware description language (HDL) is used for defining circuit architectures at the component, board, and system levels. Circuit models can be developed at a very high level of abstraction. One such language is known as register transfer level (RTL), which allows digital circuits to be described as a collection of Boolean equations, registers, control logic (e.g., if-then-else statements), and complex event sequences. Commonly used RTL languages include, for example, VHDL and Verilog.
Once the architecture design is described as an RTL implementation, that RTL implementation is then synthesized into a gate-level netlist. The resulting schematic of the gate level netlist can then be used as a guide for the overall block and function placement (floor planning), specific gate placement (pick-n-place), and layout of physical interconnections (routing). Once the implementation is achieved, it can be verified using a C-model that is derived from the specification.
FIG. 1 illustrates the flow of conventional video processing architecture design process. As can be seen, the design process starts with the applicable specification or standard, such as the H.264 standard, also known as the Advanced Video Coding (AVC) standard. This specification is a high compression digital video codec standard produced by the Joint Video Team (JVT), and is identical to ISO MPEG-4 part 10, and is herein incorporated by reference in its entirety.
The next step in the design process is the hardware architecture design. A significant problem that hardware architecture designers face is that the H.264 specification is difficult to comprehend from a designers point of view and provides little structural guidelines. In this sense, there is a disconnect between the specification and hardware architecture design portions of the design process. After the hardware architecture design phase, the design process proceeds to RTL implementation. A C-model based in the specification is used to performance test the implementation and hardware architecture design.
Substantial time and resources are generally expended during the implementation phase of the hardware architecture design. Once at the implementation stage of the design process, only limited changes can be made at the implementation level without penalty. In addition, any changes necessary to the hardware architecture design after the implementation process generally come with a heavy penalty. In particular, once the hardware architecture design is adjusted, the implementation process must be repeated, at the cost of additional time and resources. Thus, if the verification process fails, the design process must be started over and is repeated until a proposed hardware architecture design is verified.
What is needed, therefore, are design techniques that allow video processing hardware designers to effectively employ the requirements of the H.264 specification (or other appropriate video processing standard) during the hardware architecture design phase of the design process. Such techniques would eliminate or otherwise reduce costly multiple passes through the implementation and verification portions of the design process.